Design Clocked Sequential Circuit Using Jk Flip Flop

Sequential Circuits

The basis of all sequential circuits is a circuit called a flip-flop, and the simplest flip-flop circuit is called the S-R flip-flop, with the letters S and R meaning set and reset.

From: Electronics Simplified (Third Edition) , 2011

Asynchronous sequential logic

John Crowe , Barrie Hayes-Gill , in Introduction to Digital Electronics, 1998

General form of a sequential circuit

Sequential circuits are essentially combinational circuits with feedback. A block diagram of a generalised sequential circuit is shown in Fig. 5.1. The generalised circuit contains a block of combinational logic which has two sets of inputs and two sets of outputs. The inputs ¹ are:

Fig. 5.1. The general form of a sequential logic circuit

•

A, the present (external) inputs to the circuit;

•

y, the inputs fed back from the outputs;

•

Z, the present (external) outputs from the combinational circuit;

•

Y, the outputs that are fed back into the combinational circuit.

Note that the outputs, Y, are fed back via the memory block to become the inputs, y, and that y are called the 'present state' variables because they determine the current state of the circuit, with Y the 'next state' variables as they will determine the next state the circuit will enter.

It is often useful to think in terms of two independent combinational circuits, one each for the two sets of outputs, Z (external) and Y (internal), as shown in Fig. 5.2. Both of these outputs will in general depend upon the external, A, and internal, y, (fed back) inputs.

Fig. 5.2. A general sequential circuit emphasising how the outputs from the combinational logic block are functions of both the external and internal inputs

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Introduction to Digital Logic Design with VHDL

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

6.15.1 Introduction

Sequential logic circuits are based on combinational logic circuit elements (AND, OR, etc.) working alongside sequential circuit elements (latches and flip-flops that will be grouped together to form registers). A generic sequential logic circuit is shown in Figure 6.65. Here the circuit inputs to the circuit are applied to the combinational logic, and the circuit outputs are derived from this combinational logic block. The sequential logic circuit elements store an output from the combinational logic, and this is fed back to the combinational logic to form the present state of the circuit. The output from the combinational logic forming the inputs to the sequential logic circuit elements in turn forms the next state of the circuit. The circuit changes from the present state to the next state on a clock control input. Commonly the D latch and D-type flip-flop are used, and these sequential circuit elements will be used in this text (rather than other forms of latch and flip-flop such as the S-R, toggle, and J-K flip-flops).

Figure 6.65. Generic sequential logic circuit (counter or state machine)

Such sequential logic circuit designs create counters and state machines. The state machines are based on either the Moore machine or Mealy machine, as shown in Figure 6.66.

Figure 6.66. Moore and Mealy state machines

The diagrams shown in Figure 6.66 are a modification of the basic structure identified in Figure 6.65 by separating the combinational logic block into two blocks, one to create the next state logic (inputs to the state register, an array of flip-flops, that store the state of the circuit) and the output logic. In the Moore machine, the outputs are a function of only the current state (the outputs from the state register), whereas in the Mealy machine, the outputs are a function of the current state and the current inputs.

The types of circuits considered here are synchronous circuits in that activity will occur under the control of a clock control input. All of the circuit operation will be tied to this clock input. A number of possible circuits can be formed to produce the required circuit functionality.

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Clock-driven sequential circuits

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. WOODS MA, DPhil , in Digital Logic Design (Fourth Edition), 2002

8.13 The 'one-hot' state assignment

Sequential circuits described by ASM charts may be implemented using a 'one-hot' state assignment with the intention of reducing design time. The number of states required by the machine is defined by the ASM chart. In this type of assignment only one flip-flop will be high at any given instant of time. If the chart has n states then n flip-flops are required, one for every state. For an 8-state machine eight flip-flops are required, whilst using the state assignment technique described earlier in this chapter only three flip-flops are needed.

The technique provides an alternative method of implementation which in the following example employs one DFF per state. When using the technique, encoding of states is not needed and the problems associated with state assignment do not arise. However, a slightly different method of tabulation will be used.

The ASM chart for a 4-state machine is shown in Figure 8.22 along with the tabulation of the present and next states. For each of the state transitions, the corresponding transition signal is tabulated. For example, if the present state of the machine is S₁ and the transition (input) signal is XY = 1 then the machine will make the transition from S₁ to S₂. The remaining two terms in the equation for S₀ are obtained in a similar manner. The next-state equations are:

Figure 8.22. 'One-hot' implementation technique (a) ASM chart (b) Transition table (c) Machine implementation

$\begin{array}{l}{S}_0=(\overline{X}+\overline{Y})S_1+S_2+XZ{S}_3\\ S1=XZ{S}_0\\ S_2=XY{S}_1+(\overline{X}+\overline{Z})S_3+X\overline{Z}{S}_0\\ S_3=\overline{X}{S}_0\end{array}$

Implementation of the machine is shown in Figure 8.22.

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Sequential Logic Design

Sarah L. Harris , David Harris , in Digital Design and Computer Architecture, 2022

Putting It All Together

Sequential circuits have setup and hold time constraints that dictate the maximum and minimum delays of the combinational logic between flip-flops. Modern flip-flops are usually designed so that the minimum delay through the combinational logic can be 0—that is, flip-flops can be placed back-to-back. The maximum delay constraint limits the number of consecutive gates on the critical path of a high-speed circuit because a high clock frequency means a short clock period.

Example 3.10

Timing Analysis

Ben Bitdiddle designed the circuit in Figure 3.42. According to the data sheets for the components he is using, flip-flops have a clock-to-Q contamination delay of 30 ps and a propagation delay of 80 ps. They have a setup time of 50 ps and a hold time of 60 ps. Each logic gate has a propagation delay of 40 ps and a contamination delay of 25 ps. Help Ben determine the maximum clock frequency and whether any hold time violations could occur. This process is called timing analysis.

Figure 3.42. Sample circuit for timing analysis

Solution

Figure 3.43(a) shows waveforms illustrating when the signals might change. The inputs, A to D, are registered, so they only change shortly after CLK rises.

Figure 3.43. Timing diagram: (a) general case, (b) critical path, (c) short path

The critical path occurs when B = 1, C = 0, D = 0, and A rises from 0 to 1, triggering n1 to rise, X′ to rise, and Y′ to fall, as shown in Figure 3.43(b). This path involves three gate delays. For the critical path, we assume that each gate requires its full propagation delay. Y′ must set up before the next rising edge of the CLK. Hence, the minimum cycle time is

(3.18) $T_c\ge t_{\mathit{pcq}}+3t_{\mathit{pd}}+t_{\text{setup}}=80+3\times 40+50=250\text{ps}$

The maximum clock frequency is f _c = 1/T _c = 4   GHz.

A short path occurs when A = 0 and C rises, causing X′ to rise, as shown in Figure 3.43(c). For the short path, we assume that each gate switches after only a contamination delay. This path involves only one gate delay, so it may occur after t _ccq + t _cd = 30 + 25 = 55   ps. But recall that the flip-flop has a hold time of 60 ps, meaning that X′ must remain stable for 60 ps after the rising edge of CLK for the flip-flop to reliably sample its value. In this case, X′ = 0 at the first rising edge of CLK, so we want the flip-flop to capture X = 0. Because X′ did not hold stable long enough, the actual value of X is unpredictable. The circuit has a hold time violation and may behave erratically at any clock frequency.

Example 3.11

Fixing Hold Time Violations

Alyssa P. Hacker proposes to fix Ben's circuit by adding buffers to slow down the short paths, as shown in Figure 3.44. The buffers have the same delays as other gates. Help her determine the maximum clock frequency and whether any hold time problems could occur.

Figure 3.44. Corrected circuit to fix hold time problem

Solution

Figure 3.45 shows waveforms illustrating when the signals might change. The critical path from A to Y is unaffected because it does not pass through any buffers. Therefore, the maximum clock frequency is still 4   GHz. However, the short paths are slowed by the contamination delay of the buffer. Now, X′ will not change until t _ccq + 2t _cd = 30 + 2 × 25 = 80 ps. This is after the 60 ps hold time has elapsed, so the circuit now operates correctly.

Figure 3.45. Timing diagram with buffers to fix hold time problem

This example had an unusually long hold time to illustrate the point of hold time problems. Most flip-flops are designed with t _hold < t _ccq to avoid such problems. However, some high-performance microprocessors, including the Pentium 4, use an element called a pulsed latch in place of a flip-flop. The pulsed latch behaves like a flip-flop but has a short clock-to-Q delay and a long hold time. In general, adding buffers can usually, but not always, solve hold time problems without slowing the critical path.

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Event driven circuits

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. WOODS MA, DPhil , in Digital Logic Design (Fourth Edition), 2002

9.1 Introduction

Some sequential circuits are driven by events rather than by a train of clock pulses. For example, a digital alarm will be activated by the event that raised the alarm. In this example it is the event that drives the logic, and since the events are frequently irregular occurrences, such a circuit is referred to as an asynchronous sequential circuit or, perhaps more meaningfully, as an event driven circuit.

Asynchronous circuits are also called fundamental mode circuits. The main characteristic of this type of circuit is that only one input is allowed to change at any given instant. Simultaneous changes are forbidden as, indeed, are changes that may take place before the circuit reaches a stable condition after the preceding change. This is clearly different from the behaviour of a synchronous sequential circuit, where inputs changing at arbitrary times are allowed and state changes are activated by the repetitive clock signal.

There are two conditions in which an asynchronous circuit may exist, namely stable and unstable. The total state of the circuit at a given time is defined by the logical values of the inputs and the present state of the circuit. If the next state is the same as the present one the circuit is in a stable condition. If, however, an input changes, the circuit may move to an unstable condition and at some later time the state variables will have taken on their new values such that the next state has become the present state, and stability has been restored.

When designing asynchronous circuits, the designer has to eliminate the possibility of the occurrence of static hazards, dynamic hazards, essential hazards and races, in order to avoid circuit malfunction. These problems, with the exception of static hazards, do not exist in synchronous circuits since they are always designed to reach a steady-state condition before the next clock pulse arrives. Bearing in mind the design difficulties, perhaps the main advantage of asynchronous circuits is that they can work at their own speed and are not constrained to work within the time limits imposed on them by a repetitive clock signal.

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Answers to selected self-assessment questions and problems

John Crowe , Barrie Hayes-Gill , in Introduction to Digital Electronics, 1998

Self-assessment

5.1: Sequential circuits have 'memory' because their outputs depend, in part, upon past outputs. 5.2: Combinational logic plus 'memory'. 5.3: For n-outputs from 'memory', and m-external inputs; have: 2 ⁿ internal and 2 ^{m + n} possible total states. 5.4: Memory elements in synchronous circuits are flip-flops which are clocked. Asynchronous circuits are unclocked. 5.5: The internal inputs and outputs must match (as they are connected). 5.6: Only one input can change at a time (fundamental mode operation). 5.7: 'Cutting' the connection between internal inputs and outputs. 5.9: (a) Horizontal; (b) vertical. 5.10: Oscillation. 5.11: Non-critical races do not affect final output; critical races do.

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Introduction to Digital Logic Design

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

5.5.1 Introduction

Sequential logic circuits are based on combinational logic circuit elements (AND, OR, etc.) working alongside sequential circuit elements (latches and flip-flops). A generic sequential logic circuit is shown in Figure 5.36. Here, the circuit inputs are applied to and the circuits outputs are derived from a combinational logic block. The sequential logic circuit elements store an output from the combinational logic that is fed back to the combinational logic input to constitute the present state of the circuit. The output from the combinational logic that forms the inputs to the sequential logic circuit elements constitutes the next state of the circuit. These sequential logic circuit elements are grouped together to form registers. The circuit changes state from the present state to the next state on a clock control input (as happens in a synchronous sequential logic circuit). Commonly the D-latch and D-type flip-flop are used (rather than other forms of latch and flip-flop such as the S-R, toggle, and J-K flip-flops), and they will be discussed in this text. The output from the circuit is taken from the output of the combinational logic circuit block.

Figure 5.36. Generic sequential logic circuit (counter or state machine)

In general, sequential logic circuits may be asynchronous or synchronous:

1.

Asynchronous sequential logic. This form of sequential logic does not use a clock input signal to control the timing of the circuit. It allows very fast operation of the sequential logic, but its operation is prone to timing problems where unequal delays in the logic gates can cause the circuit to operate incorrectly.

2.

Synchronous sequential logic. This form of sequential logic uses a clock input signal to control the timing of the circuit. The timing of changes in states in the sequential logic is designed to occur either on the edge of the clock input when flip-flops are used, or at a particular logic level, as when latches are used. State changes that occur on the edge of the clock input, as when flip-flops are used, occur either on a 0 to 1 rise, referred to as positive edge triggered, or on a 1 to 0 fall, referred to as negative edge triggered.

In this text, only synchronous sequential logic will be considered.

An alternative view for the generic sequential logic circuit in Figure 5.36, is shown in Figure 5.37. Here, the combinational logic is separated into input and output logic. Both views are commonly used in the description of sequential logic circuits.

Figure 5.37. Alternative view for the generic sequential logic circuit

In designing the synchronous sequential logic circuit (from now on simply referred to as the sequential logic circuit), the designer must consider both the type of sequential logic circuit elements (latch or flip-flop) and the combinational logic gates. The design uses the techniques previously discussed—Boolean logic expressions, truth tables, schematics, and Karnaugh maps—to determine the required input combinational logic (the next state logic) and determine the required output combinational logic.

The sequential logic circuit will form one of two types of machines:

1.

In the Moore machine, the outputs are a function only of the present state only.

2.

In the Mealy machine, the outputs are a function of the present state and the current inputs.

In addition, the sequential logic circuit will be designed either to react to an input or to be autonomous. In an autonomous sequential logic circuit, there are no inputs (apart from the clock and reset/set) to control the operation of the circuit, so the circuit moves through states under the control of only the clock input. An example of an autonomous sequential logic circuit is a straight binary up-counter that moves through a binary count sequence taking the outputs directly from the sequential logic circuit element outputs. A sequential logic circuit can also be designed to react to an input: a sequential logic circuit that reacts to an input is called a state machine in this text.

Sequential logic circuit design follows a set design sequence aided by:

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state transition diagram, which provides a graphical means to view the states and the transitions between states

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state transition table, similar in appearance to a combinational logic truth table, which identifies the current state outputs and the possible next state inputs to the sequential logic circuit elements.

As an example, consider a circuit that is to detect the sequence 1001 on a serial bitstream data input and produce a logic 1 output when the sequence has been detected, as shown in Figure 5.38. The state machine will have three inputs—one Data_In that is to be monitored for the sequence and two control inputs, Clock and Reset—and one output, Detected. Such a state machine could be used in a digital combinational lock circuit.

Figure 5.38. 1001 sequence detector

An example state transition diagram for this design is shown in Figure 5.39. The circuit is to be designed to start in State 0 and has five possible states. With these five states, if D-type flip-flops are to be used, then there will need to be a need for three flip-flops (producing eight possible states although only five will be used when each state is to be represented by one value of a straight binary count sequence 0, 1, 2, 3, 4, 0, etc.). The arrangement for the state transition diagram is:

Figure 5.39. "1001" sequence detector state transition diagram (Moore machine)

1.

The circles identify the states. The name of the state (the state identifier) and the outputs for each state are placed within the circle. Each state is referred to as a node.

2.

The transition between states uses a line with the arrow end identifying the direction of movement. Each line starts and ends at a node.

3.

Each line is accompanied by an identifier that identifies the logical value of the input (here Data_In) that controls the state machine to go to the next particular state.

This form of the state transition diagram is for a Moore machine and in this form the outputs for each state are identified within the circles. The alternative to the Moore machine is the Mealy machine. In the Mealy machine, the outputs for a particular state are identified on the lines connecting the states along with the identifier.

The state transition table (also referred to as a present state/next state table) for the 1001 sequence detector state diagram is shown in Table 5.29. Each possible input condition has its own column, and each row contains the present state and the next state for each possible input condition. The Detected output is defined in the truth table shown in Table 5.30.

Table 5.29. State transition table for the 1001 sequence detector

	Data_In = 0	Data_In = 1
Present state	Next state	Next state
State 0	State 0	State 1
State 1	State 1	State 2
State 2	State 3	State 1
State 3	State 0	State 4
State 4	State 0	State 1

Table 5.30. Detected output for the 1001 sequence detector

State	Detected
State 0	0
State 1	0
State 2	0
State 3	0
State 4	1

Using the circuit architecture shown in Figure 5.37, the input and output combinational logic blocks are created. Each state is created using the outputs from the sequential logic circuit element block. Flip-flops form a register whose outputs produce a binary value that defines one of the states. It is common to create the states as a straight binary count. Using n-flip-flops, 2ⁿ states are possible in the register output. However, any count sequence could be used. For example, one-hot encoding uses n-flip-flops to represent n states. In the one-hot encoding scheme, to change from one state to the next, only two flip-flop outputs will change (the first from a 1 to a 0, and the second from a 0 to a 1). The advantage of this scheme is less combinational logic to create the next state values.

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Counting and Correcting

Ian Sinclair , in Electronics Simplified (Third Edition), 2011

Publisher Summary

The basis of all sequential circuits is a circuit called a flip-flop, and the simplest flip-flop circuit is called the S-R flip-flop, (set and reset). A flip-flop is a circuit, whose output(s) change state for some sequence of inputs, and which remain unchanged until another sequence of inputs is used. Unlike a gate, simply changing the inputs to a sequential circuit does not necessarily change the outputs. Sequential circuits are the other important digital type, used in counting and for memory actions. The simplest type is the S-R flip-flop (or latch) whose output(s) can be set by one pair of inputs and reset by reversing each input. Sequential circuits can be created using gates, emphasizing the importance of the gate as a fundamental digital circuit. The master-slave J-K flip-flop uses two programming inputs labeled J and K, whose voltages determine how the flip-flop will operate when a clock pulse is applied. Frequency meters and counter/timer circuits are obvious applications of counter circuits to measuring devices, and they have completely replaced older methods. Frequency synthesizers are another application of counter circuits, and this type of action is now extensively used in radio and television receivers to produce the correct oscillator frequency for a superhet receiver circuit. The more advanced methods of error detection and correction, ranging from simple Hamming codes through CRC to ReedeSolomon, all make use of added bits in a block of data and mathematical methods that allow the position of an error to be found. These methods also allow for error correction.

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Digital Building Blocks

Sarah L. Harris , David Harris , in Digital Design and Computer Architecture, 2022

Scan Chains*

Shift registers are often used to test sequential circuits, using a technique called scan chains. Testing combinational circuits is relatively straightforward. Known inputs called test vectors are applied, and the outputs are checked against the expected result. Testing sequential circuits is more difficult because the circuits have state. Starting from a known initial condition, a large number of cycles of test vectors may be needed to put the circuit into a desired state. For example, testing that the most significant bit of a 32-bit counter advances from 0 to 1 requires resetting the counter, then applying 2³¹ (about two billion) clock pulses!

Don't confuse shift registers with the shifters from Section 5.2.5. Shift registers are sequential logic blocks that shift in a new bit on each clock edge. Shifters are unclocked combinational logic blocks that shift an input by a specified amount.

To solve this problem, designers like to be able to directly observe and control all of the machine's state. This is done by adding a test mode in which the contents of all flip-flops can be read out or loaded with desired values. Most systems have too many flip-flops to dedicate individual pins to read and write each flip-flop. Instead, all flip-flops in the system are connected together into a shift register called a scan chain. In normal operation, the flip-flops load data from their D input and ignore the scan chain. In test mode, the flip-flops serially shift their contents out and shift in new contents using S _in and S _out. The load multiplexer is usually integrated into the flip-flop to produce a scannable flip-flop. Figure 5.39 shows the schematic and symbol for a scannable flip-flop and illustrates how the flops are cascaded to build an N-bit scannable register.

Figure 5.39. Scannable flip-flop: (a) schematic, (b) symbol, and (c) N-bit scannable register

For example, the 32-bit counter could be tested by shifting in the pattern 011111…111 in test mode, counting for one cycle in normal mode, then shifting out the result, which should be 100000…000. This requires only 32 + 1 + 32 = 65 cycles.

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The digital computer

Martin Plonus , in Electronics and Communications for Scientists and Engineers (Second Edition), 2020

8.3.2 Clock

In Section 7.5 we showed that in order for sequential logic circuits to operate in an orderly fashion they were regulated by a clock signal. Similarly for a computer, the timing control is provided by an external clock (which can be built into the processor circuit or provided externally by, for example, a crystal oscillator circuit) ³ that produces a clock signal which looks like a square wave shown in Fig. 7.20b. This regular and steady signal can be considered the heartbeat of the system. All computer operations are synchronized by it. The square-wave clock signal provides two states (top and bottom of the pulse) and two edges (one rising, one falling) per period that are used in switching and timing various operations. Edge-triggering is preferred as this leads to devices with more accurate synchronization since edges are present only a short time in comparison with the tops or bottoms of pulses.

Each operation in a particular computer takes a number of clock cycles. For example, the low-end microcontroller 8052 requires 12 clock cycles to access data in external memory. The Motorola 68040, on the other hand, requires three of its bus clock (BCLK) cycles to access external memory and possibly more to access words and long words that are not aligned properly. The 8052 requires six clock cycles to fetch an instruction and 6 more to execute it. In many computers, the operations are overlapped for sequences of instructions. For example, in the 8052 the fetch cycle of the next instruction can be done at the same time the execution phase of the first instruction occurs; this is because the execution phase happens completely inside the CPU of the computer and so does not interfere with the fetching of the next instruction from memory (Fig. 8.4). If an instruction requires operands from external memory, additional memory fetch cycles are required after the instruction itself has been fetched. Complex instructions, like multiply and divide can require extra execution cycles. Processor speed is usually stated in millions of clock cycles per second, or megahertz (MHz) or more recently in billions of clock cycles per second, or gigahertz (GHz). No instruction can take less than one clock cycle–if the processor completes the instruction before the cycle is over, the processor must wait. Common processors operate at speeds from 8 to 1000   MHz (1   GHz). At 8   MHz, each clock cycle lasts 0.125 millionths of a second (0.125   μs); at 100   MHz, 0.01/μs; and at 300   MHz, 0.0033/μs   =   3.3   ns (nanoseconds).

Fig. 8.4. A CPU instruction cycle.

In addition to raw megahertz speed, smart design augments the newest processors' capabilities. These processors contain a group of circuits that can work on several instructions at the same time—similar to a factory that has several assembly lines running at the same time. The more instructions a processor can work on at once, the faster it runs. The Motorola 68040 microprocessor, for example, can work on six instructions at once. The older 68030 is limited to four. That is why a computer with a 25   MHz 68040 is faster than one with a 25   MHz 68030.

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Design Clocked Sequential Circuit Using Jk Flip Flop

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